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Silicon Labs /EFR32BG21B020F1024IM32 /RAC_S /SYLOEN

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Interpret as SYLOEN

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https://regviz.com/r/Silicon Labs/BGM210LA22JNF/RAC_NS/SYLOEN#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (disable)SYLODIVRLOADCCLK2G4EN 0 (disable)SYLODIVRLO12G4EN 0 (disable)SYLODIVRLO22G4EN 0 (disable)SYLODIVTLO0DBM2G4AUXEN 0 (disable)SYLODIVTLO0DBM2G4EN 0 (disable)SYLODIVTLO20DBM2G4AUXEN 0 (disable)SYLODIVTLO20DBM2G4EN

SYLODIVTLO20DBM2G4AUXEN=disable, SYLODIVTLO0DBM2G4AUXEN=disable, SYLODIVRLO22G4EN=disable, SYLODIVRLOADCCLK2G4EN=disable, SYLODIVTLO0DBM2G4EN=disable, SYLODIVTLO20DBM2G4EN=disable, SYLODIVRLO12G4EN=disable

Fields

SYLODIVRLOADCCLK2G4EN

SYLODIVRLOADCCLK2G4EN

0 (disable): undefined

1 (enable): undefined
SYLODIVRLO12G4EN

SYLODIVRLO12G4EN

0 (disable): undefined

1 (enable): undefined
SYLODIVRLO22G4EN

SYLODIVRLO22G4EN

0 (disable): undefined

1 (enable): undefined
SYLODIVTLO0DBM2G4AUXEN

SYLODIVTLO0DBM2G4AUXEN

0 (disable): undefined

1 (enable): undefined
SYLODIVTLO0DBM2G4EN

SYLODIVTLO0DBM2G4EN

0 (disable): undefined

1 (enable): undefined
SYLODIVTLO20DBM2G4AUXEN

SYLODIVTLO20DBM2G4AUXEN

0 (disable): undefined

1 (enable): undefined
SYLODIVTLO20DBM2G4EN

SYLODIVTLO20DBM2G4EN

0 (disable): undefined

1 (enable): undefined

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data